1. Field of the Invention
The present invention relates to semiconductor packages, and more particularly, to a multi-substrate region-based package and a method for fabricating the same.
2. Description of Related Art
Conventional leadframe-based semiconductor package, such as a quad flat package (QFP), is fabricated by preparing a leadframe comprising a die pad and a plurality of leads, mounting a chip on the die pad, forming a plurality of bonding wires for electrically connecting bond pads formed on the chip to the corresponding leads, and encapsulating the chip and the bonding wires by an encapsulant.
Such conventional leadframe-based semiconductor package however has a drawback that the leads serving as input/output (I/O) connections can only be disposed around the encapsulant, that is, the number of I/O connections provided is limited by the size of the encapsulant, thereby failing to fulfill the requirement of further increase in I/O connections for the electronic products nowadays. Accordingly, a ball grid array (BGA) semiconductor package has been developed.
FIG. 1 shows a conventional BGA semiconductor package. In FIG. 1, a substrate 111 having a plurality of traces formed on a top surface and a bottom surface thereof is used, wherein the traces on the top surface are electrically connected to the traces on the bottom surface by internal conductive traces and vias (not shown) in the substrate 111. A chip 112 is mounted on the top surface of the substrate 111, and a plurality of bond pads 112a formed on the chip 112 are electrically connected to the traces on the top surface of the substrate 111 by a plurality of bonding wires 112. An encapsulant 114 is formed on the substrate 111, for encapsulating the chip 112 and the bonding wires 113. And, a plurality of solder balls 115 are implanted to a plurality of ball pads 111a formed at ends of the traces on the bottom surface of the substrate 111, allowing the chip 112 to be electrically connected to an external device via the solder balls 115. By this arrangement, more I/O connections can be obtained by means of the entire layout of traces and ball pads of the substrate 111.
However, the conventional BGA package configuration has gone out of date due to its poor compatibility with the progress trends of having lower profile, more functions and shorter life span for the electronic products. Therefore, high-density packaging (HDP) technologies, which can effectively fabricate package products with reduced sizes, have become a major focus in the industry.
Development of electronic engineering begins with developing an “element”, then progresses to a stage of aggregating a plurality of “elements” (such as assembling a plurality of integrated circuits (IC) into a system), and eventually progresses to a stage of “integration”, thereby attaining to the HDP technologies such as System on Chip (SoC), System in a Package (SiP) and Multi-Chip Package (MCP).
Each of the aforesaid HDP technologies has its own advantages and disadvantages. SoC integrates a processor unit, a memory and an analog signal processing unit all in a single chip. In some cases where SoC is not applicable, SiP (which integrates two or more chips in a single package) is used as an alternative choice. Generally, SoC is relatively more cost-effective, increases yield, and has less complex packaging than SiP. By contrast, SiP may package a plurality of chips, which are fabricated by different techniques and/or made of different materials, into a system while maintaining good compatibility among the chips.
Moreover, the difference between MCP and SiP is that MCP focuses more on aggregation of high-density memories in a vertical (Z) direction, thereby providing a small packaging area. On the other hand, SiP focuses more on packaging of high performance multi-functional chips in a horizontal (X-Y) direction, thereby providing good heat dissipation and reliability of the package.
Therefore, the problem to be solved herein is to develop a packaging technique which may combine the advantages of the aforesaid HDP technologies while eliminating their disadvantages.